MB40C318PFV 查看數據表（PDF） - Fujitsu

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MB40C318PFV

8-bit 140 MSPS A/D Converter

Fujitsu 

MB40C318

s TIMING CHART 4

Two-phase CLK input mode (CLKA, CLKB)

• DVDDI = DVDD

• CLKEP = “L” (DVSS), CLKEN = “H” (DVDD) or CLKEP = “H” (DVDD), CLKEN = “L” (DVSS)

• CLKA = CLKB = 70 MHz (max)

• CKSEL = “L” (AVSS)

• DSEL = “L (DVSS)

• RESET = “H” (DVDD) or RESET = “L” (DVSS)

• CE = “L” (AVSS)

• OE = “L” (DVSS)

VIHD

tWD−

CLKA input

VILD

tWD+

VIHD

CLKB input

VILD

N(Ach)

tWD+

tr

tf

DVDD − 0.5 V

0.5 V

1.5 V

tWD−

tr

tf

DVDD − 0.5 V

0.5 V

1.5 V

N + 1(Bch) N + 2(Ach) N + 3(Bch) N + 4(Ach) N + 5(Bch) N + 6(Ach) N + 7(Bch)

VINA input

tAD

tAD

VOHD

DA0 to DA7

VOLD

VOHD

DB0 to DB7

VOLD

N−6

N−4

N−5

VOHD

CLKOA

VOLD

VOHD

CLKOB

VOLD

N−3

tpdD(max)

tpdD(typ)

tpdD(min)

N

N−2

DVDD − 0.4 V

0.4 V

tpdD(max)

tpdD(typ)

tpdD(min)

N+1

N−1

tpdDO(max)

tpdDO(typ)

tpdDO(min)

DVDD − 0.4 V

0.4 V

DVDD − 0.4 V

0.4 V

tpdDO(max)

tpdDO(typ)

tpdDO(min)

DVDD − 0.4 V

0.4 V

• VINA input — Sampling (A ch) at CLKA falling

Sampling (B ch) at CLKB falling

• DA0 to DA7 — Output (after 2.5 CLK + tpdD from Sampling) at CLKA rising

• DB0 to DB7 — Output (after 2.5 CLK + tpdD from Sampling) at CLKB rising

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