IDT70V05L15J(2000) 查看數據表（PDF） - Integrated Device Technology

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IDT70V05L15J
(Rev.:2000)

HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM

Waveform of Read Cycles(5)

ADDR

CE

OE

R/W

DATAOUT

BUSYOUT

tAA (4)

tACE (4)

tAOE (4)

tLZ (1)

Military, Industrial and Commercial Temperature Ranges

tRC

VALID DATA(4)

tBDD(3,4)

tOH

tHZ (2)

2941 drw 07

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first CE or OE.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no

relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

6.942

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