IDT70V05L(1996) 查看數據表（PDF） - Integrated Device Technology

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IDT70V05L
(Rev.:1996)

HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT70V05S/L

HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)

A0-A2

SEM

I/O0

R/W

OE

VALID ADDRESS

tAW

tWR

tEW

tDW

DATAIN

VALID

tAS

tWP

tDH

tSAA

tOH

VALID ADDRESS

tACE

tSOP

DATAOUT

VALID(2)

tSWRD

tAOE

Write Cycle

Read Cycle

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NOTES:

1. CE = VIH for the duration of the above timing (both write and read cycle).

2. "DATAOUT VALID" represents all I/O's (I/O0-I/O7) equal to the semaphore value.

TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)

A0"A"-A2"A"

SIDE(2) “A”

W R/ "A"

MATCH

SEM"A"

A0"B"-A2"B"

SIDE(2) “B”

W R/ "B"

tSPS

MATCH

SEM"B"

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NOTES:

1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.

2. “A” may be either left or right port. “B” is the opposite port from “A”.

3. This parameter is measured from R/WA or SEMA going high to R/WB or SEMB going HIGH.

4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.

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