IDT70V07L55G8 查看數據表（PDF） - Integrated Device Technology
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IDT70V07L55G8 Datasheet PDF : 19 Pages
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IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
70V07X25
Com'l
& Ind
70V07X35
Com'l
& Ind
70V07X55
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address
____
25
____
35
____
45
ns
tBDA
BUSY Disable Time from Address
____
25
____
35
____
45
ns
tBAC
BUSY Access Time from Chip Enable
____
25
____
35
____
45
ns
tBDC
BUSY Disable Time from Chip Enable
tAPS
Arbitration Priority Set-up Time(2)
____
25
____
35
____
45
ns
5
____
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
BUSY TIMING (M/S - VIL)
____
35
____
40
____
50
ns
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSY(5)
0
____
0
____
0
____
ns
20
____
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
____
55
____
65
____
85
ns
____
50
____
60
____
80
ns
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
2943 tbl 13
Timing Waveform of Write with Port-to-Port Read and BUSY(2,4,5)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDW
tDH
DATAIN "A"
tAPS (1)
VALID
ADDR"B"
MATCH
BUSY"B"
tBAA
tBDA
tWDD
DATAOUT "B"
NOTES:
tDDD (3)
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
11
tBDD
VALID
2943 drw 13
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