MX7672LP10(2012) 查看數據表（PDF） - Maxim Integrated

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MX7672LP10
(Rev.:2012)

High-Speed 12-Bit ADC With External Reference Input Part

Maxim Integrated 

MX7672

High-Speed 12-Bit ADC With External

Reference Input Part

the conversion time is 3.125µs when fCLK = 4MHz, 5µs

when fCLK = 2.5MHz, and 10µs when fCLK = 1.25MHz.

The delay from the falling edge of RD to the falling edge

of CLKIN must not be less than 100ns to ensure the 12.5

clock cycle conversion time (Figure 7). This gives the

external sample-and-hold 1.5 clock cycles to settle from

hold transients. An additional 1/2 clock cycle of settling

can be allowed for the sample-­and-hold by having RD go

low at the falling edge of CLKIN. This results in a 13-cycle

conversion time (3.25µs, 5.2µs, and 10.4µs).

Digital Interface

Timing and Control

CS and RD control conversion start and data-read opera-

tions. Figure 8 shows the logic equivalent for the con-

version and the data-output control circuitry. A logic-low

at both inputs starts a conversion. Once a conversion

is in progress, it cannot be restarted. The BUSY output

remains low during the entire conversion cycle.

Figures 9 and 10 outline the two interface modes (slow

memory and ROM). Slow-memory mode is for µPs that

can be forced into a wait state for periods as long as the

MX7672 conversion time. ROM mode is for µPs that can-

not be forced into a wait state. In both interface modes, a

processor read operation to the ADC address starts the

conversion. In the ROM mode, a second read operation

accesses the conversion result.

Slow-Memory Mode

The timing diagram in Figure 9 illustrates slow-memory

mode, which is designed for µPs with a wait state. CS

and RD go low, triggering a conversion, and are kept low

until the conversion is complete. BUSY responds by going

low, and data from the previous conversion remains on

the three-state data outputs. At conversion end, BUSY

returns high, and the output latches transfer the new

conversion results to the three-state data outputs. The µP

completes the read operation by taking CS and RD high.

ROM Mode

The ROM mode avoids placing the µP into a wait state.

A conversion begins with a read operation. While CS and

RD are low, data from the last conversion is available on

the data outputs. A second read operation reads the new

data and begins the conversion process again. A delay

at least as long as the MX7672 conversion time must be

allowed between read operations. The data on the output

bus is in a parallel format in either mode.

Application Hints

Digital Bus Noise

If the data bus connected to the ADC is active during a

conversion, coupling from the data pins to the ADC com-

parator may cause LSBs of error. Using slow-memory

mode avoids this problem by placing the µP into a wait

state during the conversion. In ROM mode, if the data bus

is active during the conversion, use three-state drivers to

isolate the bus from the ADC.

Figure 7. MX7672 RD and CLKIN for Synchronous Operation

and Conversion Time of 12.5 Clock Cycles

Figure 8. Logic for Control Inputs CS and RD Internal

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