ISPPAC-CLK5320S-01T64I 查看數據表（PDF） - Lattice Semiconductor

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ISPPAC-CLK5320S-01T64I

In-System Programmable, Zero-Delay Universal Fan-Out Buffer, Single-Ended

Lattice Semiconductor 

Lattice Semiconductor

ispClock5300S Family Data Sheet

DC Electrical Characteristics – Input/Output Loading

Symbol

Parameter

Conditions

ILK

Input Leakage

IPU

Input Pull-up Current

Note 1

Note 2

REFSEL, PLL_BYPASS

IPD

Input Pull-down Current

OEX, OEY, 2.5V CMOS Logic Standard

OEX, OEY, & 3.3V CMOS Logic Standard

IOLK

Tristate Leakage Output

Note 4

CIN

Input Capacitance

Notes 2, 3, 5

Note 6

1. Applies to clock reference inputs when termination ‘open’.

2. Applies to TDI, TMS and RESET inputs.

3. Applies to REFSEL and PLL_BYPASS, OEX, OEY.

4. Applies to all logic types when in tristated mode.

5. Applies to OEX, OEY, TCK, RESET inputs.

6. Applies to REFA_REFP, REFB_REFN, FBK.

Min.

—

—

—

—

—

—

—

—

Typ.

—

80

120

120

200

—

8

10

Max.

±10

120

150

150

400

±10

10

11

Units

µA

µA

µA

µA

µA

µA

pF

pF

Switching Characteristics – Timing Adders for I/O Modes

Adder Type

Description

tIOI Input Adders2

LVTTL_in

Using LVTTL Standard

LVCMOS18_in

Using LVCMOS 1.8V Standard

LVCMOS25_in

Using LVCMOS 2.5V Standard

LVCMOS33_in

Using LVCMOS 3.3V Standard

SSTL2_in

Using SSTL2 Standard

SSTL3_in

Using SSTL3 Standard

HSTL_in

Using HSTL Standard

eHSTL_in

Using eHSTL Standard

LVDS_in

Using LVDS Standard

LVPECL_in

Using LVPECL Standard

tIOO Output Adders1, 3

LVTTL_out

Output Configured as LVTTL Buffer

LVCMOS18_out

Output Configured as LVCMOS 1.8V Buffer

LVCMOS25_out

Output Configured as LVCMOS 2.5V Buffer

LVCMOS33_out

Output Configured as LVCMOS 3.3V Buffer

SSTL18_out

Output Configured as SSTL18 Buffer

SSTL2_out

Output Configured as SSTL2 Buffer

SSTL3_out

Output Configured as SSTL3 Buffer

HSTL_out

Output Configured as HSTL Buffer

eHSTL_out

Output Configured as eHSTL Buffer

tIOS Output Slew Rate Adders1

Slew_1

Output Slew_1 (Fastest)

Slew_2

Output Slew_2

Slew_3

Output Slew_3

Slew_4

Output Slew_4 (Slowest)

1. Measured under standard output load conditions – see Figures 6 and 7.

2. All input adders referenced to LVTTL.

3. All output adders referenced to SSTL/HSTL/eHSTL.

Min.

—

—

—

—

Typ.

0.00

0.10

0.00

0.00

0.00

0.00

1.15

1.10

0.60

0.60

0.25

0.25

0.25

0.25

0.00

0.00

0.00

0.00

0.00

0.00

475

950

1900

Max.

—

—

—

—

Units

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ps

ps

ps

ps

8

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