µPD16335
SWITCHING CHARACTERISTICS (TA = 25°C, VDD1 = 5.0 V, VDD2 = 130 V, VSS1 = VSS2 = 0 V, logic CL
= 15 pF, driver CL = 50 pF, tr = tf = 6.0 ns)
Parameter
Transmission Delay Time
Rise Time
Fall Time
Maximum Clock Frequency
Input Capacitance
Symbol
Conditions
tPHL1 CLK ↓ → A/B
tPLH1
tPHL2 CLK ↑ (LE = H) → O1 to O96
tPLH2
tPHL3
BLK → O1 to O96
tPLH3
tPHL4
PC → O1 to O96
tPLH4
tPHZ
OE → O1 to O96
tPZH
RL = 10 kΩ
tPLZ
tPZL
tTLH
O1 to O96
tTLZ
RL = 10 kΩ
tTZH
O1 to O96
tTHL
O1 to O96
tTHZ
RL = 10 kΩ
tTZL
O1 to O96
fmax. When data is read, duty 50%
cascade connection, Duty 50%
CI
MIN.
25
16
TYP.
MAX.
55
55
180
180
165
165
160
160
300
180
300
180
120
3
120
150
3
150
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
ns
MHz
MHz
pF
TIMING REQUIREMENT (TA = –40 to +85°C, VDD1 = 4.5 to 5.5 V, VSS1, 2 = 0 V, tr = tf = 6.0 ns)
Parameter
Clock Pulse Width
Latch Enable Pulse Width
Blank Pulse Width
PC Pulse Width
OE Pulse Width
Data Setup Time
Data Hold Time
Latch Enable Time 1
Latch Enable Time 2
Symbol
PWCLK
PWLE
PWBLK
PWPC
PWOE RL = 10 kΩ
tsetup
thold
tLE1
tLE2
Condition
MIN. TYP. MAX. Unit
20
ns
20
ns
200
ns
200
ns
3.3
µs
7
ns
10
ns
20
ns
20
ns
8