KB3920 查看數據表（PDF） - Unspecified

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KB3920

Keyboard Controller

Unspecified 

KB3920 Keyboard Controller Datasheet

PMU Control / Configuration

7

Enter STOP mode by writing this bit = 1, the same as 8051 PCON

STOP

6

Enter IDLE mode by writing this bit = 1, the same as 8051 PCON

IDLE

0Ch PMUCFG

Enable auto return to normal clock as async-wakeup event coming

5

in Ultra Low clock state. Async-wakeup including LPC cycles and

GPW U.

4

MUST be set to ‘1’ to enable wakeup feature.

2Fh FFh

Enable SCI to be one of wake up interrupt source

3

8051 interrupt source will always exit Ultra Low clock to normal

clock

2

Enable LPC cycle and Watchdog interrupt wake up from STOP

mode

1

Enable GPWU wake up from STOP mode

0

Enable Interrupt wake up from IDLE mode

Clock Configuration

Enable Flash (ISA / SPI) Interface Clock From External Pin

(GPIO59)

The Flash I/F clock is default from internal PLL (66Mhz). The

7

R/W internal PLL 66Mhz clock duty cycle is not 50-50%, so that the clock

high and low limit of SPI flash should be noted. A 66Mhz SPI flash

may not be usable in the PLL 64Mhz configuration. But a 100Mhz

SPI flash may be usable.

Flash (ISA / SPI) Interface Clock Control

1: full speed (Internal clock is 66(+-%25) Mhz )

6

R/W 0: half speed (default, ½ of supplied clock)

SPI clock is 16Mhz if CLKCFG set to 8/4 Mhz;

SPI clock is stopped when 8051 in IDLE if CLKCFG.0 is set.

5

R/W Enable PLL to generate a good 32.768Mhz. (default reset PLL)

0Dh CLKCFG

4

R/W Enable PLL enter low power state in STOP mode

00h FFh

8051 / Peripherals Normal Run Clock Selection.

10: 22 / 8 Mhz

01: 16 / 8 Mhz (default)

3~2

R/W

00: 8 / 4 Mhz

Clock rate is fixed at 2/1Mhz when 8051 is in IDLE mode if

CLKCFG.0 is set.

The flash interface (SPI or ISA) is fixed at 32.768 Mhz or higher by

CLKCFG.6 setting.

Enable Peripheral Auto Slow Clock Control to be 1 Mhz.

1

R/W The Peripheral’s clock will be running at 1-Mhz when no host is

accessing.

Enable 8051 IDLE Mode Slow Clock Control to be 2 / 1 Mhz.

0

R/W

When 8051 enters IDLE state, the clock of 8051 and peripherals will

be changed automatically to 2 / 1 Mhz. And the flash interface clock

will be stopped if this bit is set.

EC Extended Write IO data

0Eh

EXTIO

7~0 R/W Read this byte to get the host write extended IO data.

00h FFh

DAC0 output value

10h

DAC0

7 – 0 R/W Output DAC0 data

00h FFh

DAC1 output value

11h

DAC1

7 – 0 R/W Output DAC1 data

00h FFh

DAC2 output value

12h

DAC2

7 – 0 R/W Output DAC2 data

00h FFh

13h

DAC3 DAC3 output value

00h FFh

Copyright©2006, ENE Technology Inc.

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