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D0 PL
D1
D2
D3
CPD
CPU
SD
Q
T FF1
Q
CD
SD
Q
T FF2
Q
CD
SD
Q
T FF3
Q
CD
SD
Q
T FF4
Q
CD
TCU TCD
MR
Q0
Q1
Q2
Q3
001aak069
Fig 2. Logic diagram