HEF40193B 查看數據表（PDF） - NXP Semiconductors.
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HEF40193B Datasheet PDF : 20 Pages
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HEF40193B
4-bit up/down binary counter
Rev. 8 — 18 November 2011
Product data sheet
1. General description
The HEF40193B is a 4-bit synchronous up/down binary counter. The counter has a
count-up clock input (CPU), a count-down clock input (CPD), an asynchronous parallel
load input (PL), four parallel data inputs (D0 to D3), an asynchronous master reset input
(MR), four counter outputs (Q0 to Q3), an active LOW terminal count-up (carry) output
(TCU), and an active LOW terminal count-down (borrow) output (TCD).
The counter outputs change state on the LOW-to-HIGH transition of either clock input.
However, for correct counting, both clock inputs cannot be LOW simultaneously. The
outputs TCU and TCD are normally HIGH. When the circuit has reached the maximum
count state of ‘15’, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW.
TCU will stay LOW until CPU goes HIGH again. Likewise, output TCD will go LOW when
the circuit is in the zero state and CPD goes LOW. When PL is LOW, the information on
D0 to D3 is asynchronously loaded into the counter. A HIGH on MR resets the counter
independent of all other input conditions. The counter stages are of a static toggle type
flip-flop.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1. Ordering information
All types operate from 40 C to +85 C.
Type number
Package
Name
Description
HEF40193BP
DIP16
plastic dual in-line package; 16 leads (300 mil)
HEF40193BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT38-4
SOT109-1
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