HV400MJ883 查看數據表（PDF） - Intersil

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HV400MJ883

High Current MOSFET Driver

Intersil 

HV400MJ/883

The bootstrap capacitor should hold at least 10x the charge

of the MOSFET and should be connected between Pins 1

and 4/5 with minimum pin lengths and spacings. Likewise,

the HV400MJ/883 should be as close to the MOSFET as

possible. Any long PC traces (parasitic inductances)

between the MOSFET gate and Pins 8 or 3/6 or between the

source and Pins 4/5 should be avoided. Inductance between

the HV400MJ/883 and the MOSFET limit the MOSFET

switching time. If they are too large, the HV400MJ/883 may

operate erratically as discussed below.

Cross Conduction Faults

It is possible to have both Q1 and the SCR on at the same

time resulting in very large cross conduction currents. The

SCR has larger current capacity so the output goes low and

the storage capacitor is discharged. The conditions that

cause cross conduction and precautions are discussed

below.

Minimum Off Time

The SCR requires a recovery time before voltage can be

reapplied without it switching back on. Figure 13 shows how

this SCR recovery time, called “minimum off time” (tOR), is a

function of the load capacitance. If the input voltage goes

high before this recovery time is complete, the SCR will

switch back on.

Note that reverse current flowing through the SCR, for

example due to load inductance ringing, extends the

minimum off time. Since the minimum off time is really

dependent upon how much stored charge remains in the

SCR when the anode (Pin 3/6) is taken positive, it may vary

for different applications. Figure 13 indirectly shows that the

minimum off time increases with larger currents. It also

increases at elevated temperatures as shown in Figure 14.

Excessive ringing increases the minimum off time since the

stored charge doesn’t begin to dissipate until the current

drops below 10mA for the last time. Rising anode voltage

acts on the internal SCR capacitance to generate its own

triggering current. The excess stored charge increases this

capacitance. Faster rise times and/or higher voltages also

increase the amount of internal trigger current from the inter-

nal capacitance so applications with larger dV/dt require

longer minimum off times.

The minimum off time must be considered for all occur-

rences of SCR current. For example, in a half bridge switch

mode power supply, there are two MOSFETs connected to

the transformer primary. Assume that the high side MOSFET

switch is off. When the low side MOSFET switch is turned

on, the HV400MJ/883 driving the high side MOSFET will

have to sink gate current from CGD and will have to source

gate current when the low side MOSFET switches back off.

Both of these current pulses will try to flow through Pin 3/6

since the Pin 8 output is turned off. Sourcing current from

Pins 3/6 through the SCR is possible, the Pin 3/6 voltage

becoming negative with respect to Pins 4/5 (See Figure 8).

But a better practice would be to connect a Schottky diode

between Pins 4/5 (anode) and 3/6 (cathode) so reverse cur-

rent does not flow through the SCR.

False SCR Triggering

The SCR may be triggered inadvertently. The output may

overshoot the input due to inductive loading or over driving

the output NPN (allowing it to saturate). Whenever Pin 6 is

more positive than Pin 2 by 1V, the SCR is triggered on.

Also, if the output rises too rapidly, greater than 0.5V/ns, the

SCR may self trigger. Both issues are resolved by minimiz-

ing the load inductance and inserting sufficient resistance,

usually 0.1Ω to 10Ω, between Pin 8 and the load.

A very fast negative going input voltage can result in minimum

off times of about 2.5µs. If the output can not keep up with the

falling input, the stored charge of diode D4 is transferred into

the base of Q2. This excess charge in Q2 must have time to

dissipate. Otherwise, when Pin 3/6 goes positive, Q2 will turn

on and trigger the SCR. An external diode in series with Pin 2,

as shown in Figure 1, will prevent D4 from discharging into the

base of Q2 but that will also reduce the output voltage by the

forward voltage of that diode.

Internal Diodes

The internal diodes connected to Pin 7 are provided for

convenience but may not be suitable for large currents.

Since they are part of the integrated circuit, they are

physically small, operate at high current densities, and have

long recovery times. Figure 15 shows that their forward

characteristics degrade above 100mA. In addition, Figure 16

shows their reverse recovery charge as a function of forward

current. The product of this charge, the applied reverse

voltage and the frequency is the additional power dissipation

due to the diodes. For stored charge calculations, use the

peak forward current within 100ns of the application of

reverse bias. In addition to the extra power dissipation, the

capacitance of these diodes may extend the switching delay

times.

Power Dissipation Calculations

The power required to drive the MOSFET is the product of

its total gate charge times the gate supply voltage (maximum

voltage on HV400MJ/883 Pin 1, 2 or 7) times the frequency.

Assuming that the MOSFET gate resistance is negligible,

this power is dissipated within the HV400MJ/883. If resistors

are placed between the HV400MJ/883 and the MOSFET,

then some of the power is dissipated in the resistors, the per-

centage depending upon the ratio of resistors to

HV400MJ/883 output impedance.

There are two other sources of power dissipation to

consider. First there is the power in R3 which is the product

of the input Pin 2 current and voltage (with no output current)

times the duty cycle. Second is the product of the Pin 7

diode stored charge, which is dependent upon the forward

current, times the applied diode reverse voltage times the

frequency. This information is available from Figure 3 and

Figure 16 in this data sheet.

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