T7121 查看數據表（PDF） - Agere -> LSI Corporation

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T7121

HDLC Interface for ISDN (HIFI-64)

Agere -> LSI Corporation 

Data Sheet

April 1997

Description (continued)

T7121 HDLC Interface for ISDN (HIFI-64)

RESET

RD

WR

CS

INT

AD0—AD7

ALE

A0—A3

MICRO-

PROCESSOR

BUS

INTERFACE

MEMORY

BUFFERS

HDLC

PROCESSING

TRANSPARENT

MODE

INTERNAL

REGISTER

BANK

(R0—R15)

(AR11—AR13)

AND

PARALLEL

DATA I/O

TRANSMIT

FIFO

64 x 8

HDLC

TRANSMITTER

CONCEN-

TRATION

HIGHWAY

INTERFACE

RECEIVE

FIFO

64 x 8

HDLC

RECEIVER

TRANSPARENT

MODE

DXA

DXB/TSCA

CLKX

CLK

FS

DRA

CLKR/DRB

Figure 1. Block Diagram

5-5027

Lucent Technologies Inc.

3

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