ST7522 查看數據表（PDF） - Sitronix Technology Co., Ltd.
零件编号
产品描述 (功能)
生产厂家
ST7522 Datasheet PDF : 45 Pages
| |||
ST7522
The Accessing the Display Data RAM and the Internal Registers
Data transfer at a higher speed is ensured since the MPU is the first data read cycle (dummy) stores the read data in the
required to satisfy the cycle time (tCYC) requirement alone in
accessing the ST7522 Series. Wait time may not be
considered.
And, in the ST7522 Series chips, each time data is sent from
the MPU, a type of pipeline process between LSIs is
performed through the bus holder attached to the internal
data bus. Internal data bus.
For example, when the MPU writes data to the display data
RAM, once the data is stored in the bus holder, then it is
written to the display data RAM before the next data write
bus holder, and then the data is read from the bus holder to
the system bus at the next data read cycle.
There is a certain restriction in the read sequence of the
display data RAM. Please be advised that data of the
specified address is not generated by the read instruction
issued immediately after the address setup. This data is
generated in data read of the second time. Thus, a dummy
read is required whenever the address setup
or write cycle operation is conducted.
This relationship is shown in Figure 2.
cycle. Moreover, when the MPU reads the display data RAM,
WR
Data
Writing
N
N+1
N+2
N+3
Bus Holder
Write Signal
N
N+1
N+2
N+3
WR
RD
Data
Address
Preset
Read Signal
Column
Address
Bus Holder
Reading
N
N
n
n+1
Preset N
N
Increment N+1
n
N+2
n+1
n+2
Address
Set #n
Dummy
Read
Figure 2
Data Read
#n
Data Read
#n+1
Ver 1.0c
10/45
2002/07/10
Share Link: 