PEB2084 查看數據表（PDF） - Siemens AG
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PEB2084 Datasheet PDF : 72 Pages
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PEB 2084
2.2 Interfaces
PEB 2084, QUAT-S, provides four independent S/T interfaces, one IOM-2 interface and
one JTAG boundary scan test interface.
2.2.1 S/T Interface
Frame Structure
One frame consists of 48 bits, at a nominal bit rate of 192 kbit/s. Thus each frame carries
two octets of B1, two octets of B2 and 4 bits of D-channel, according to the B1+B2+D
structure defined for the ISDN basic access (the total user data rate is 144 kbit/s). The
beginning of the frame is marked with a F-bit using a code violation (no Mark inversion).
The frame structures for data downstream (from network to subscriber) and for data
upstream (from subscriber to network) are shown in figure 3.
48 Bits in 250 µs
DL. F L.
B1
E D A FA N
B2
EDM
B1
EDS
B2
E D L. F L.
0
NT TE 1
0
2 Bits Offset
DL. F L.
B1
L. D L.FA L.
0
TE NT 1
0
t
F = Framing Bit
L = DC Balancing Bit
D = D-Channel Bit
E = D-Echo-Channel Bit
FA = Auxiliary Framing Bit or Q-Bit
B2
L. D L.
B1
L. D L.
B2
N = Bit set to a Binary Value N = FA
B1 = Bit within B Channel 1
B2 = Bit within B Channel 2
A = Bit used for Activation
S = Subchannel SC1 through SC5 bit position
M = Multiframing Bit
L. D L. F L.
ITD02330
Figure 3
Frame Structure at Reference Points S and T (CCITT I.430)
The E-bit (= Echo bit to the D-channel bit) can be controlled via C/I channel and may be
used to carry the “available” / “blocked” information sent by ELIC, PEB 20550. Refer to
chapter 3.3.3.
Semiconductor Group
14
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