MPC92433 查看數據表（PDF） - Freescale Semiconductor

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MPC92433

1428 MHz Dual Output LVPECL Clock Synthesizer

Freescale Semiconductor 

Table 15. CMD (0xF0): PLL Command (Write-Only)

Command

INC

DEC

LOAD

GET

Op-Code

xxxx0001b

(0x01)

xxxx0010b

(0x02)

xxxx0100b

(0x04)

xxxx1000b

(0x08)

Description

Increase internal PLL frequency

M:=M+1

Decrease internal PLL frequency

M:=M-1

Update the PLL divider config.

PLL divider M, N, P:=PLL_L, PLL_H

Update the configuration registers

PLL_L, PLL_H:=PLL divider M, N, P

I2C — Register Access in Parallel Mode

The MPC92433 supports the configuration of the

synthesizer through the parallel interlace (PLOAD = 0) and

serial interface (PLOAD = 1). Register contents and the

divider configurations are not changed when the user

switches from parallel mode to serial mode. However, when

switching from serial mode to parallel mode, the PLL dividers

immediately reflect the logical state of the hardware pins

M[9:0], NA[2:0], NB, and P.

Applications using the parallel interface to obtain a PLL

configuration can use the serial interface to verify the divider

settings. In parallel mode (PLOAD = 0), the MPC92433

allows read-access to PLL_L and PLL_H through I2C (if

PLOAD = 0, the current PLL configuration is stored in PLL_L,

PLL_H. The GET command is not necessary and also not

supported in parallel mode). After changing from parallel to

serial mode (PLOAD = 1), the last PLL configuration is still

stored in PLL_L, PLL_H. The user now has full write and read

access to both configuration registers through the I2C bus

and can change the configuration at any time.

Table 16. PLL Configuration in Parallel and Serial Modes

PLL

Configuration

M[9:0]

NA[2:0]

NB

P

LOCK status

Parallel

Set pins M9–M0

Set pins NA2...NA0

Set pin NB

Set pin P

LOCK pin 26

Serial (Registers

PLL_L, PLL_H)

M[9:0] (R/W)

NA[2:0] (R/W)

NB (R/W)

P (R/W)

LOCK (Read only)

Programming the I2C Interface

Table 17. I2C Slave Address

Bit 7 6 5 4

Value 1 0 1 1

3

2

1

0

0 Pin Pin R/W

ADR1 ADR0

The 7-bit I2C slave address of the MPC92433 synthesizer

is a combination of a 5-bit fixed addresses and two variable

bits which are set by the hardware pins ADR[1:0]. Bit 0 of the

MPC92433 slave address is used by the bus controller to

select either the read or write mode. ’0’ indicates a

transmission (I2C-WRITE) to the MPC92433. ’1’ indicates a

request for data (I2C-READ) from the synthesizer. The

hardware pins ADR1 and ADR0 and should be individually

set by the user to avoid address conflicts of multiple

MPC92433 devices on the same I2C bus.

Write Mode (R/W = 0)

The configuration registers are written by the bus

controller by the initiation of a write transfer with the

MPC92433 slave address (first byte), followed by the address

of the configuration register (second byte: 0x00, 0x01 or

0xF0), and the configuration data byte (third byte). This

transfer may be followed by writing more registers by sending

the configuration register address followed by one data byte.

Each byte sent by the bus controller is acknowledged by the

MPC92433. The transfer ends by a stop bit sent by the bus

controller. The number of configuration data bytes and the

write sequence are not restricted.

Table 18. Complete Configuration Register Write Transfer

1 bit

7 bits

1 bit 1 bit

Start

Slave address R/W

10110xx(1)

0

ACK

Master

Master

Mast Slave

1. xx = state of ADR1, ADR0 pins

8 bits

&PLL_H

0x01

Master

1 bit

ACK

8 bits

Config-Byte 1

Data

1 bit

ACK

Slave

Master

Slave

8 bits

&PLL_L

0x00

Master

1 bit

ACK

8 bits

Config-Byte 2

Data

1 bit

ACK

1 bit

Stop

Slave

Master

Slave Mast

Advanced Clock Drivers Devices

Freescale Semiconductor

MPC92433

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