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MPC9230EI

800MHz Low Voltage PECL Clock Synthesizer

Integrated Device Technology 

MPC9230 Data Sheet

800MHZ LOW VOLTAGE PECL CLOCK SYNTHESIZER

Substituting N for the four available values for N (1, 2, 4, 8) yields:

Table 11. Output Frequency Range for fXTAL = 16 MHz

N

Output

Output

FOUT

1 0 Value

Frequency

Range for

Frequency

Range for

TA = 0°C to 70°C TA = –40°C to 85°C

FOUT

Step

00 2

M 200 – 400 MHz 200 – 375 MHz 1 MHz

0 1 4 M÷2 100 – 200 MHz 100 – 187.5 MHz 500 kHz

1 0 8 M÷4 50 – 100 MHz 50 – 93.75 MHz 250 kHz

1 1 1 2 ⋅ M 400 – 800 MHz 400 – 750 MHz 2 MHz

Example Frequency Calculation for an 16 MHz Input Frequency

If an output frequency of 131 MHz was desired, the following

steps would be taken to identify the appropriate M and N values.

According to Table 11, 131 MHz falls in the frequency set by a value

of 4, so N[1:0] = 01. For N = 4, the output frequency is FOUT = M ÷

2 and M = FOUT x 2. Therefore M = 2 x 131 = 262, so M[8:0] =

010000011. Following this procedure a user can generate any whole

frequency between 50 MHz and 800 MHz. Note than for

N > 2 fractional values of can be realized. The size of the

programmable frequency steps (and thus the indicator of the

fractional output frequencies achievable) will be equal to:

fSTEP = fXTAL ÷ 8 ÷ N

APPLICATIONS INFORMATION

Using the Parallel and Serial Interface

The M and N counters can be loaded either through a parallel or

serial interface. The parallel interface is controlled via the P_LOAD

signal such that a LOW to HIGH transition will latch the information

present on the M[8:0] and N[1:0] inputs into the M and N counters.

When the P_LOAD signal is LOW, the input latches will be

transparent and any changes on the M[8:0] and N[1:0] inputs will

affect the FOUT output pair. To use the serial port, the S_CLOCK

signal samples the information on the S_DATA line and loads it into

a 14 bit shift register. Note that the P_LOAD signal must be HIGH for

the serial load operation to function. The Test register is loaded with

the first three bits, the N register with the next two and the M register

with the final eight bits of the data stream on the S_DATA input. For

each register the most significant bit is loaded first (T2, N1 and M8).

A pulse on the S_LOAD pin after the shift register is fully loaded will

transfer the divide values into the counters. The HIGH to LOW

transition on the S_LOAD input will latch the new divide values into

the counters. Figure 4 illustrates the timing diagram for both a

parallel and a serial load of the MPC9230 synthesizer. M[8:0] and

N[1:0] are normally specified once at power-up through the parallel

interface, and then possibly again through the serial interface. This

approach allows the application to come up at one frequency and

then change or fine-tune the clock as the ability to control the serial

interface becomes available.

Using the Test and Diagnosis Output TEST

The TEST output provides visibility for one of the several internal

nodes as determined by the T[2:0] bits in the serial configuration

stream. It is not configurable through the parallel interface. Although

it is possible to select the node that represents FOUT, the LVPECL

compatible TEST output is not able to toggle fast enough for higher

output frequencies and should only be used for test and diagnosis.

The T2, T1 and T0 control bits are preset to ‘000' when P_LOAD is

LOW so that the LVPECL compatible FOUT outputs are as jitter-free

as possible. Any active signal on the TEST output pin will have

detrimental affects on the jitter of the PECL output pair. In normal

operations, jitter specifications are only guaranteed if the TEST

output is static. The serial configuration port can be used to select

one of the alternate functions for this pin. Most of the signals

available on the TEST output pin are useful only for performance

verification of the MPC9230 itself; however, the PLL bypass mode

may be of interest at the board level for functional debug. When

T[2:0] is set to 110 the MPC9230 is placed in PLL bypass mode. In

this mode the S_CLOCK input is fed directly into the M and N

dividers. The N divider drives the FOUT differential pair and the M

counter drives the TEST output pin. In this mode the S_CLOCK

input could be used for low speed board level functional test or

debug. Bypassing the PLL and driving FOUT directly gives the user

more control on the test clocks sent through the clock tree. Table 12

shows the functional setup of the PLL bypass mode. Because the

S_CLOCK is a CMOS level, the input frequency is limited to 200

MHz. This means the fastest the FOUT pin can be toggled via the

S_CLOCK is 50 MHz as the divide ratio of the Post-PLL divider is 4

(if N = 1). Note that the M counter output on the TEST output will not

be a 50% duty cycle.

Table 12. Test and Debug Configuration for TEST

T[2:0]

T2 T1 T0

000

TEST Output

14-bit shift register out(1)

0 0 1 Logic 1

0

1

0 fXTAL ÷ 16

0 1 1 M-Counter out

1

0

0 FOUT

1 0 1 Logic 0

1 1 0 M-Counter out in PLL-bypass mode

1

1

1 FOUT ÷ 4

1. Clocked out at this rate of S_CLOCK.

Table 13. Debug Configuration for PLL Bypass(1)

Output

FOUT

TEST

Configuration

S_CLOCK ÷ N

M-Counter out(2)

1. T[2:0]=110. AC specifications do not apply in PLL bypass mode.

2. Clocked out at the rate of S_CLOCK÷(2⋅N).

MPC9230 REVISION 8 MARCH 29, 2010

9

©2010 Integrated Device Technology, Inc.

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