MC74HC161AN(2000) 查看數據表（PDF） - ON Semiconductor

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MC74HC161AN
(Rev.:2000)

Presettable Counters

ON Semiconductor 

P0 3

P1 4

P2 5

P3 6

ENABLE P 7

ENABLE T 10

RESET 1

LOAD 9

CLOCK 2

T0

R

Q0

C

C

LOAD

LOAD Q0

P0

T1

R

Q1

C

C

LOAD

LOAD Q1

P1

T2

R

Q2

C

C

LOAD

LOAD Q2

P2

14 Q0

13 Q1

12

Q2

R

LOAD

LOAD

C

C

T3

R

Q3

C

C

LOAD

LOAD

P3

11 Q3

VCC = PIN 16

GND = PIN 8

15

RIPPLE

CARRY

OUT

The flip–flops shown in the circuit diagrams are Toggle–Enable flip–flops. A Toggle–

Enable flip–flop is a combination of a D flip–flop and a T flip–flop. When loading data from

Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of

the flip–flop. The logic level at the Pn input is then clocked to the Q output of the flip–flop

on the next rising edge of the clock.

A logic zero on the Reset device input forces the internal clock (C) high and resets the Q

output of the flip–flop low.

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