M5M4V4265TP-5 查看數據表（PDF） - MITSUBISHI ELECTRIC
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M5M4V4265TP-5
MITSUBISHI ELECTRIC
M5M4V4265TP-5 Datasheet PDF : 31 Pages
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MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
FUNCTION
In addition to EDO Mode, normal read, write and read-modify-
write operations the M5M4V4265CXX provides a number of other
functions, e.g., RAS-only refresh, and delayed-write. The input
conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
RAS
Inputs
LCAS UCAS
Lower byte read
Upper byte read
ACT
ACT
ACT
NAC
NAC
ACT
Word read
ACT ACT ACT
Lower byte write
ACT ACT NAC
Upper byte write
ACT NAC ACT
Word write
ACT ACT ACT
RAS only refresh
ACT NAC NAC
Hidden refresh
ACT ACT ACT
CAS before RAS (Extended *) refresh ACT
ACT
ACT
Self refresh *
ACT ACT ACT
Stand-by
NAC DNC DNC
Note : ACT : active, NAC : nonactive, DNC : don' t care, OPN : open
W
NAC
NAC
NAC
ACT
ACT
ACT
DNC
NAC
DNC
DNC
DNC
OE
ACT
ACT
ACT
NAC
NAC
NAC
DNC
ACT
DNC
DNC
DNC
DQ1~DQ8
DOUT
OPN
DOUT
DIN
DNC
DIN
OPN
DOUT
OPN
OPN
OPN
Input/Output
DQ9~DQ16
OPN
DOUT
DOUT
DNC
DIN
DIN
OPN
DOUT
OPN
OPN
OPN
BLOCK DIAGRAM
ROW ADDRESS
STROBE INPUT RAS
LOWER BYTE CONTROL
COLUMN ADDRESS LCAS
STROBE INPUT
UPPER BYTE CONTROL UCAS
COLUMN ADDRESS
STROBE INPUT
WRITE CONTROL
INPUT
W
CLOCK GENERATOR
CIRCUIT
LOWER
UPPER
A0
A1
A2
A3
ADDRESS INPUTS A4
A5
A6
A7
A8
A0~A8
COLUMN DECODER
ROW &
COLUMN
ADDRESS
BUFFER A0~
ROW
A8 DECODER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
MEMORY CELL
(4,194,304 BITS)
(8)LOWER
DATA IN
BUFFER
(8)LOWER
DATA OUT
BUFFER
(8)UPPER
DATA IN
BUFFER
(8)UPPER
DATA OUT
BUFFER
2 M5M4V4265CJ,TP-5,-5S:under development
VCC (3.3V)
VSS (0V)
DQ1
DQ2
DQ8
LOWER DATA
INPUTS /
OUTPUTS
VCC (3.3V)
VSS (0V)
DQ9
DQ10
DQ16
UPPER DATA
INPUTS /
OUTPUTS
VCC (3.3V)
VSS (0V)
OE
OUTPUT
INPUT
ENABLE
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