M13S64164A-5BIG 查看數據表（PDF） - [Elite Semiconductor Memory Technology Inc.

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M13S64164A-5BIG

1M x 16 Bit x 4 Banks Double Data Rate SDRAM

[Elite Semiconductor Memory Technology Inc. 

ESMT

M13S64164A

Operation Temperature Condition -40°C~85°C

AC Timing Parameter & Specifications-continued

Parameter

Symbol

-5

min

max

-6

min

max

Half Clock Period

tHP

tCLmin or tCHmin

-

tCLmin or tCHmin

-

ns

DQ-DQS output hold time

tQH

tHP- tQHS

-

tHP- tQHS

-

ns

Data hold skew factor

tQHS

-

0.45

-

0.5

ns

ACTIVE to PRECHARGE

command

tRAS

40

120K

42

120K

ns

Row Cycle Time

tRC

60

-

60

-

ns

AUTO REFRESH Row Cycle

Time

tRFC

70

-

72

-

ns

ACTIVE to READ,WRITE

delay

tRCD

15

-

18

-

ns

PRECHARGE command

period

tRP

15

-

18

-

ns

ACTIVE to READ with

AUTOPRECHARGE

tRAP

15

120K

18

120K

ns

command

ACTIVE bank A to ACTIVE

bank B command

tRRD

10

-

12

-

ns

Write recovery time

tWR

15

-

18

-

ns

Write data in to READ

command delay

tWTR

2

-

2

-

tCK

Col. Address to Col. Address

delay

tCCD

1

-

1

-

tCK

Average periodic refresh

interval

tREFI

-

15.6

-

15.6

us

Write preamble

tWPRE

0.25

-

0.25

-

tCK

Write postamble

tWPST

0.4

0.6

0.4

0.6

tCK

DQS read preamble

tRPRE

0.9

1.1

0.9

1.1

tCK

DQS read postamble

tRPST

0.4

0.6

0.4

0.6

tCK

Clock to DQS write preamble

setup time

tWPRES

0

-

0

-

ns

Load Mode Register /

Extended Mode register

tMRD

2

-

1

-

tCK

cycle time

Exit self refresh to READ

command

tXSRD

200

-

200

-

tCK

Exit self refresh to

non-READ command

tXSNR

75

-

75

-

ns

Autoprecharge write

recovery+Precharge time

tDAL

(tWR/tCK)

+

(tRP/tCK)

(tWR/tCK)

+

tCK

(tRP/tCK)

Elite Semiconductor Memory Technology Inc.

Publication Date : Mar. 2009

Revision : 1.0

7/49

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