M13S64164A-5BIG 查看數據表（PDF） - [Elite Semiconductor Memory Technology Inc.

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M13S64164A-5BIG

1M x 16 Bit x 4 Banks Double Data Rate SDRAM

[Elite Semiconductor Memory Technology Inc. 

ESMT

M13S64164A

Operation Temperature Condition -40°C~85°C

Burst

Length

2

4

8

Burst Address Ordering for Burst Length

Starting

Address (A2, A1,A0)

Sequential Mode

Interleave Mode

xx0

0, 1

0, 1

xx1

1, 0

1, 0

x00

0, 1, 2, 3

0, 1, 2, 3

x01

1, 2, 3, 0

1, 0, 3, 2

x10

2, 3, 0, 1

2, 3, 0, 1

x11

3, 0, 1, 2

3, 2, 1, 0

000

0, 1, 2, 3, 4, 5, 6, 7

0, 1, 2, 3, 4, 5, 6, 7

001

1, 2, 3, 4, 5, 6, 7, 0

1, 0, 3, 2, 5, 4, 7, 6

010

2, 3, 4, 5, 6, 7, 0, 1

2, 3, 0, 1, 6, 7, 4, 5

011

3, 4, 5, 6, 7, 0, 1, 2

3, 2, 1, 0, 7, 6, 5, 4

100

4, 5, 6, 7, 0, 1, 2, 3

4, 5, 6, 7, 0, 1, 2, 3

101

5, 6, 7, 0, 1, 2, 3, 4

5, 4, 7, 6, 1, 0, 3, 2

110

6, 7, 0, 1, 2, 3, 4, 5

6, 7, 4, 5, 2, 3, 0, 1

111

7, 0, 1, 2, 3, 4, 5, 6

7, 6, 5, 4, 3, 2, 1, 0

DLL Enable / Disable

The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to

normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is

enable automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.

Output Drive Strength

The normal drive strength for all outputs is specified to be SSTL_2, Class II. M13S64164A also support a weak drive strength

option, intended for lighter load and/or point-to-point environments.

Mode Register Set

0

1

CLK

CLK

2

3

4

5

6

7

8

COMMAND

Prech arg e

All Banks

*1

Mode

Register Set

An y

Com m an d

tCK

t *2

RP

*1 : MRS can be issued only at all banks precharge state.

*2 : Minimum tRP is required to issue MRS command.

Elite Semiconductor Memory Technology Inc.

Publication Date : Mar. 2009

Revision : 1.0

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