HYB3165805TL-50 查看數據表（PDF） - Siemens AG

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HYB3165805TL-50

8M x 8-Bit Dynamic RAM (4k & 8k Refresh, EDO-version)

Siemens AG 

HYB3164(5)805J/T(L)-50/-60

8M x 8 EDO-DRAM

Read Cycle:

RAS

V IH

V IL

CAS

Address

WE

OE

I/O

(Inputs)

I/O

(Outputs)

V IH

V IL

V IH

V IL

V IH

V IL

V IH

V IL

V IH

V IL

VOH

VOL

Write Cycle:

V IH

WE

V IL

OE

V IH

V IL

I/O

(Inputs)

V IH

V IL

I/O

V

(Outputs)

V

IH

IL

tRAS

tRP

tCSR

tCHR

tWRP

tWRH

tWRP

tWRH

tCP

tRSH

tCAS

tRAL

t t ASC

CAH

Column

tAA

tRCS

tCAC

tOEA

tASR

Row

tRRH

tRCH

tDZC

tDZO

tCLZ

tCDD

tODD

tOFF

tOEZ

Data Out

tWCS

tRWL

tCWL

tWCH

tDS

tDH

Data In

HI-Z

CAS-before-RAS Refresh Counter Test Cycle

Semiconductor Group

178

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