HYB3165805TL-50 查看數據表（PDF） - Siemens AG

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HYB3165805TL-50

8M x 8-Bit Dynamic RAM (4k & 8k Refresh, EDO-version)

Siemens AG 

HYB3164(5)805J/T(L)-50/-60

8M x 8 EDO-DRAM

V

RAS

IH

VIL

V

IH

CAS

VIL

V

IH

Address VIL

V

IH

WE

VIL

V

IH

OE

VIL

V

I/O

IH

(Inputs) VIL

V

I/O

OH

(Outputs) VOL

tRC

tRAS

tRP

tASR

tCSH

tRCD

tRSH

tCAS

tRAD

tASC

tRAL

tCAH

Row

tRAH

Column

tCWL

tRWL

tWP

tCRP

tASR

.

Row

tOEH

tDZO

tDZC

tODD

tDS

tDH

tOEZ

tCLZ

tOEA

Hi-Z

Valid Data

Hi-Z

“H” or “L”

WL3

Write Cycle (OE Controlled Write)

Semiconductor Group

164

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