HEF4043B(2016) 查看數據表（PDF） - NXP Semiconductors.
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HEF4043B Datasheet PDF : 13 Pages
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Nexperia
HEF4043B
Quad R/S latch with 3-state outputs
a. Input waveform
9,
QHJDWLYH
SXOVH
9
9,
SRVLWLYH
SXOVH
9
90
WI
WU
90
W:
90
WU
WI
90
W:
DDM
9,
*
9''
'87
9(;7
92
5/
57
&/
DDM
b. Test circuit
Fig 6.
Test and measurement data is given in Table 10.
Definitions test circuit:
DUT = Device Under Test.
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VDD
5 V to 15 V
Input
VI
VDD
tr, tf
20 ns
Load
CL
50 pF
RL
1 k
VEXT
tPLH, tPHL
open
tPLZ, tPZL
VDD
tPHZ, tPZH
GND
HEF4043B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 24 March 2016
© Nexperia B.V. 2017. All rights reserved
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