HD74LV161A 查看數據表（PDF） - Renesas Electronics

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HD74LV161A

Synchronous 4-bit Binary Counter (Synchronous Clear)

Renesas Electronics 

HD74LV161A

Switching Characteristics

Item

Maximum clock

frequency

Propagation

delay time

Setup time

Hold time

Pulse width

Symbol

fmax

tPLH/tPHL

tPLH/tPHL

Count mode

tPLH/tPHL

Load mode

tPLH/tPHL

tPHL

tPHL

tsu

th

tw

Ta = 25°C

Ta = –40 to 85°C

Test

VCC = 2.5 ± 0.2 V

FROM TO

Min Typ Max Min

Max

Unit Conditions (Input) (Output)

50 90 — 40

30 60 — 25

— 11.1 16.2 1.0

— 14.3 19.2 1.0

— 11.5 17.0 1.0

— 14.7 20.0 1.0

— 13.8 20.6 1.0

— 17.0 23.6 1.0

— 10.3 15.7 1.0

— 14.0 18.7 1.0

— 11.7 17.0 1.0

— 14.7 20.0 1.0

— 11.2 16.6 1.0

— 14.4 19.6 1.0

7.5 — — 8.5

—

—

19.5

22.5

20.5

23.5

24.5

27.5

19.0

22.0

20.5

23.5

20.0

23.0

—

MHz

ns

ns

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

CLK

Q

CLK

Carry

CLK

Carry

ENT

Carry

CLR

Q

CLR

Carry

Data before CLK ↑

10.0 — — 11.5 —

LOAD before CLK ↑

9.5 — — 11.0 —

ENT, ENP before

CLK ↑

4.5 — — 4.5

—

CLR inactive before

CLK ↑

1.5 — — 1.5

—

ns

7.0 — — 7.0

—

ns

CLK H or L

7.0 — — 7.0

—

CLR L

Rev.4.00 Jun. 04, 2004 page 7 of 15

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