HCMS-2353 查看數據表（PDF） - Avago Technologies

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HCMS-2353

CMOS Extended Temperature Range 5 x 7 Alphanumeric Display

Avago Technologies 

Electrical Description

The display contains four 5 x 7 LED dot matrix characters

and two CMOS integrated circuits, as shown in Figure 1.

The two CMOS integrated circuits form an on-board 28 bit

serial-in/parallel-out shift register that will accept standard

TTL logic levels. The Data Input, pin 12, is connected to

bit position 1 and the Data Output, pin 7, is connected to

bit position 28. The shift register outputs control constant

current sinking LED row drivers. A logic 1 stored in the

shift register enables the corresponding LED row driver

and a logic 0 stored in the shift register disables the corre­

sponding LED row driver.

The electrical configuration of these CMOS IC alphanumeric

displays allows for an effective interface to a display control-

ler circuit that supplies decoded character information. The

row data for a given column (one 7 bit byte per character)

is loaded (bit serial) into the on-board 28 bit shift register

with high to low transitions of the Clock input. To load

decoded character information into the display, column

data for character 4 is loaded first and the column data

for character 1 is loaded last in the following manner. The

7 data bits for column 1, character 4, are loaded into the

on-board shift register. Next, the 7 data bits for column 1,

character 3, are loaded into the shift register, shifting the

character 4 data over one character position. This process

is repeated for the other two characters until all 28 bits of

column data (four 7 bit bytes of character column data) are

loaded into the on-board shift register. Then the column

1 input, VCOL pin 1, is energized to illuminate column 1 in

all four characters. This process is repeated for columns 2,

3, 4 and 5. All VCOL inputs should be at logic low to insure

the display is off when loading data. The display will be

blanked when the blanking input VB, pin 8, is at logic low

regardless of the outputs of the shift register or whether

one of the VCOL inputs is energized. Refer to Applica­tion

Note 1016 for drive circuit information.

COLUMN DRIVE INPUTS

COLUMN

12345

LED

MATRIX

2

LED

MATRIX

3

LED

MATRIX

4

BLANKING

CONTROL, VB

1234567

ROWS

ROWS 1-7

ROWS 1-7

CONSTANT CURRENT SINKING LED DRIVERS

ROWS 1-7

SERIAL

DATA

INPUT

1234567

CLOCK

Figure 1. Display block diagram.

ROWS 8-14

ROWS 15-21

28-BIT SIPO SHIFT REGISTER

ROWS 22-28

SERIAL

DATA

OUTPUT

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