EN5394QI 查看數據表（PDF） - Enpirion, Inc.
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EN5394QI Datasheet PDF : 19 Pages
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2.5V
Rext
250
VIN
D1
Vf ~ 2V
AGND
R3
3k
IC Package
VIN
R1
100k
To Gates
R2
100k
EN5394QI
Figure 5: Equivalent circuit of a ternary pin
(MAR1, MAR2, or M/S) input buffer. To get a
logic High on a ternary input, pull the pin to VIN
through an external resistor REXT. See Electrical
Characteristics table for some recommended
REXT values as a function of VIN and the resulting
input currents.
EXT_CLK
X1
S_IN
VFB
EN5364
S_OUT
VOUT
OUT1
X1_1
S_IN
R4
C1
VFB
EN5364
S_OUT
VOUT
OUT2
X1_2
S_IN
R6
C2
VFB
EN5364
S_OUT
VOUT
R1
GND
R5
R2
R7
R3
Figure 6: Example of synchronizing multiple EN5394QIs in a daisy chain with phase delay.
OUT3
R8
C3
R9
Delay ~ 140°
VDRAIN- 1
VDRAIN- 2
Delay ~ 120°
VDRAIN- 3
Figure 7: Example of a possible way to synchronize and use delays advantageously to minimize input ripple.
R1 ~ 39kΩ, R2 ~ 33kΩ. (Refer to Figure 6 for R1 and R2.) R3 does not matter in this case.
©Enpirion 2009 all rights reserved, E&OE
03738
14
8/21/2009
www.enpirion.com
Rev:B
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