ADJD-S371-QR999 查看數據表（PDF） - Avago Technologies
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ADJD-S371-QR999 Datasheet PDF : 23 Pages
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The master terminates the serial data transfer by sending
another unique signal to the bus called a STOP condition.
This is defined as a LOW to HIGH transition on the SDA
line while SCL is HIGH.
The bus is considered to be busy after a START (S)
condition. It will be considered free a certain time after
the STOP (P) condition. The bus stays busy if a repeated
START (Sr) is sent instead of a STOP condition.
The START and repeated START conditions are
functionally identical.
SCL
SCL
S
START CONDITION
Figure 3. START/STOP condition
P
STOP CONDITION
Data Transfer
The master initiates data transfer after a START condition.
Data is transferred in bits with the master generating
one clock pulse for each bit sent. For a data bit to be
valid, the SDA data line must be stable during the HIGH
period of the SCL clock line. Only during the LOW period
of the SCL clock line can the SDA data line change state
to either HIGH or LOW.
SDA
SCL
Figure 4. Data bit transfer
DATA VALID
DATA CHANGE
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