X40015 查看數據表（PDF） - Xicor -> Intersil

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X40015

Dual Voltage Monitor with Integrated CPU Supervisor

Xicor -> Intersil 

X40010/X40011/X40014/X40015 – Preliminary

– One bit of the slave command byte is a R/W bit. The

R/W bit of the Slave Address Byte defines the opera-

tion to be performed. When the R/W bit is a one, then

a read operation is selected. A zero selects a write

operation.

Word Address

The word address is either supplied by the master or

obtained from an internal counter. The internal counter

is undefined on a power up condition.

Operational Notes

The device powers-up in the following state:

– The device is in the low power standby state.

– The WEL bit is set to ‘0’. In this state it is not possible

to write to the device.

– SDA pin is the input mode.

– RESET/RESET Signal is active for tPURST.

Data Protection

The following circuitry has been included to prevent

inadvertent writes:

– The WEL bit must be set to allow write operations.

– The proper clock count and bit sequence is required

prior to the stop bit in order to start a nonvolatile write

cycle.

– A three step sequence is required before writing into

the Control Register to change Watchdog Timer or

Block Lock settings.

Figure 14. Sequential Read Sequence

Signals from

the Master

SDA Bus

Signals from

the Slave

S

Slave

t

Address

o

A

A

A

p

C

C

C

K

K

K

1

A

C

K

Data

(1)

Data

(2)

Data

(n-1)

Data

(n)

(n is any integer greater than 1)

REV 1.3.4 7/12/02

www.xicor.com

Characteristics subject to change without notice. 13 of 25

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