TDA7503(1999) 查看數據表（PDF） - STMicroelectronics

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TDA7503
(Rev.:1999)

DUAL DSP PLUS MICRO FOR AUDIO APPLICATIONS

STMicroelectronics 

TDA7503

Figure 7. SSI Protocol.

Frame Sync 0

Frame Sync 1

Data In

SCK

Receive

Interrupts

NETWORK MODE

Five Word Packet

Data Word

Frame Sync 0

Frame Sync 1

Data In

SCK

Receive

Interrupts

NORMAL MODE

The timing diagrams for the SSI Interface are

shown in Figure 7 for both Network and Normal

modes.

In Normal Mode the rising edge FSYNC starts the

internal bit counter to allow data to be clocked in

or out. When bit count is equal to the pro-

grammed word length the counter is reset and

the shift register is broadside loaded into the data

register. Additional SCK pulses are ignored after

the counter is reset. The next word is clocked in

or out starting with the next rising edge of

FSYNC.

In Network Mode the rising edge FSYNC starts

the internal bit counter to allow data to be clocked

in or out. When bit count is equal to the pro-

grammed word length the counter is reset and

the shift register is broadside loaded into the data

register. At this point the FSRSD bit is set indicat-

ing that a frame sync was received with that

word. After being reset the counter continues

counting, clocking in the next word. Only when

the next rising edge of FSYNC is detected is the

packet considered complete.

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