74HCT161DB,112 查看數據表（PDF） - NXP Semiconductors.
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74HCT161DB,112 Datasheet PDF : 18 Pages
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Nexperia
74HC161
Presettable synchronous 4-bit binary counter; asynchronous reset
VI
PE input
VM
GND
VI
CP input
tsu
th
VM
tsu
th
GND
VI
Dn input
tsu
th
VM
tsu
th
GND
aaa-012356
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig. 12. The data input (Dn) and parallel enable input (PE) set-up and hold times
VI
CEP, CET
input
GND
VI
CP input
VM
tsu
th
VM
tsu
th
GND
aaa-012358
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig. 13. The count enable input (CEP) and count enable carry input (CET) set-up and hold times
Table 8. Measurement points
Input
VM
0.5 × VCC
VI
GND to VCC
Output
VM
0.5 × VCC
74HC161
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 4 October 2018
© Nexperia B.V. 2018. All rights reserved
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