74HC161D(2017) 查看數據表（PDF） - NXP Semiconductors.

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74HC161D
(Rev.:2017)

Presettable synchronous 4-bit binary counter; asynchronous reset

NXP Semiconductors. 

NXP Semiconductors

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

6. Functional description

Table 3. Function table[1]

Operating Input

Output

modes

MR

CP

CEP

CET

PE

Dn

Qn

TC

Reset (clear) L

X

X

X

X

X

L

L

Parallel load H



X

X

l

l

L

L

H



X

X

l

h

H

[2]

Count

H



h

h

h

X

count

[2]

Hold

H

X

l

X

h

X

qn

[2]

(do nothing) H

X

X

l

h

X

qn

L

[1] H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition

L = LOW voltage level

l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition

qn = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition

X = don’t care

 = LOW-to-HIGH clock transition

[2] The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH)

Fig 7. State diagram

































DDD

74HC161

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 4 January 2017

© NXP Semiconductors N.V. 2017. All rights reserved.

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