74AHC32BQ-Q100 查看數據表（PDF） - Nexperia B.V. All rights reserved

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74AHC32BQ-Q100

Quad 2-input OR gate

Nexperia B.V. All rights reserved 

Nexperia

74AHC32-Q100; 74AHCT32-Q100

Quad 2-input OR gate

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

74AHC32-Q100

74AHC32D-Q100 40 C to +125 C SO14

74AHC32PW-Q100 40 C to +125 C TSSOP14

74AHC32BQ-Q100 40 C to +125 C DHVQFN14

74AHCT32-Q100

74AHCT32D-Q100 40 C to +125 C SO14

74AHCT32PW-Q100 40 C to +125 C TSSOP14

74AHCT32BQ-Q100 40 C to +125 C DHVQFN14

Description

Version

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

plastic thin shrink small outline package; 14 leads; SOT402-1

body width 4.4 mm

plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads;

14 terminals; body 2.5  3  0.85 mm

SOT762-1

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

plastic thin shrink small outline package; 14 leads; SOT402-1

body width 4.4 mm

plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads;

14 terminals; body 2.5  3  0.85 mm

SOT762-1

4. Functional diagram

1 1A

2 1B

4 2A

5 2B

9 3A

10 3B

12 4A

13 4B

Fig 1. Logic symbol

1Y 3

2Y 6

3Y 8

4Y 11

mna242

1

≥1

3

2

4

≥1

6

5

9

≥1

8

10

12

≥1

11

13

mna243

Fig 2. IEC logic symbol

A

B

Fig 3. Logic diagram (one gate)

Y

mna241

74AHC_AHCT32_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 26 March 2013

© Nexperia B.V. 2017. All rights reserved

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