XRT91L82 查看數據表（PDF） - Exar Corporation

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XRT91L82

2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

Exar Corporation 

xr

REV. P1.0.5

TRANSMITTER SECTION

NAME

LEVEL

TXDI0P

TXDI0N

TXDI1P

TXDI1N

TXDI2P

TXDI2N

TXDI3P

TXDI3N

TXDI4P

TXDI4N

TXDI5P

TXDI5N

TXDI6P

TXDI6N

TXDI7P

TXDI7N

TXDI8P

TXDI8N

TXDI9P

TXDI9N

TXDI10P

TXDI10N

TXDI11P

TXDI11N

TXDI12P

TXDI12N

TXDI13P

TXDI13N

TXDI14P

TXDI14N

TXDI15P

TXDI15N

LVDS,

LVPECL

Diff and SE

TXOP

TXON

CMLDIFF

TXSWING

/ INT

LVTTL,

LVCMOS

TYPE

I

O

I/O

PRELIMINARY

XRT91L82

2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

PIN

DESCRIPTION

P14 Transmit Parallel Data Input

P13 The 155.52 Mbps 16-bit parallel transmit data input should be

N10 applied to the transmit parallel bus simultaneously to be sam-

N9

pled at the rising edge of the TXPCLKIP/N input. The 16-bit

N13

parallel interface is multiplexed into the transmit serial output

interface, MSB first (TXDI15P/N). TXDI[15:0]P/N 100 Ω internal

N12 termination is controlled by INTERM pin or register bit. Inputs

M11 are internally biased to VDD_IO - 1V for AC coupled applica-

M10 tions. For LVPECL Single-Ended applications, either a 100K

M14 VBB bias reference must be provided or the SE_REF pin can

M13 also be used to bias and connected all the negative polarity "N"

pins.

L10

NOTE: The XRT91L82 can accept 166.63 Mbps 16-bit parallel

L9

transmit data input for Forward Error Correction (FEC)

L13

Applications.

L12

K12

K11

J14

K14

J10

K10

J13

J12

H9

J9

H12

H11

G11

G10

F12

G12

G8

G7

A6 Transmit Serial Data Output

A5 The transmit serial data output stream is generated by multi-

plexing the 16-bit parallel transmit data input into a 2.488 Gbps

serial data output stream. In Forward Error Correction, the

transmit serial data output stream is 2.666 Gbps.

D10 Transmit Serial CML Output Swing Mode

Hardware Mode Selects the generated transmit serial CML

Output swing to the optical module.

"Low" = Low Swing CML Mode

"High" = High Swing CML Mode

This pin is provided with an internal pull-up.

Host Mode This pin is functions as the microprocessor Inter-

rupt Output.

NOTE: This pin becomes an open drain output in Host Mode

and requires an external pull-up resistor.

8

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