X5328P-2.7 查看數據表（PDF） - Intersil

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产品描述 (功能)

生产厂家

X5328P-2.7

CPU Supervisor with 32Kbit SPI EEPROM

Intersil 

X5328, X5329

Figure 3. VTRIP Programming Sequence Flow Chart

VTRIP Programming

Execute

Reset VTRIP

Sequence

Set VCC = VCC Applied =

Desired VTRIP

New VCC Applied =

Old VCC Applied + Error

Execute

Set VTRIP

Sequence

Apply 5V to VCC

Decrement VCC

(VCC = VCC - 10mV)

New VCC Applied =

Old VCC Applied - Error

Execute

Reset VTRIP

Sequence

NO

RESET pin

goes active?

YES

Error ≥ Emax

Emax = Maximum Desired Error

Measured VTRIP -

Desired VTRIP

Error > Emax

Error < Emax

DONE

Figure 4. Sample VTRIP Reset Circuit

4.7K

VTRIP

Adj.

Program

NC

+

1

8

2

7

3 X5328/29 6

4

5

VP

NC 4.7K

RESET

NC

10K

10K

Reset VTRIP

Test VTRIP

Set VTRIP

6

FN8132.1

October 17, 2005

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