WM8771 查看數據表（PDF） - Wolfson Microelectronics plc
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WM8771 Datasheet PDF : 44 Pages
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WM8771
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AUDIO DATA SAMPLING RATES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. The external master system clock can be applied directly through the MCLK input pin
with no software configuration necessary. In a system where there are a number of possible sources
for the reference clock it is recommended that the clock source with the lowest jitter be used to
optimise the performance of the ADC and DAC.
The master clock for WM8771 supports audio sampling rates from 128fs to 768fs, where fs is the
audio sampling frequency (DACLRC or ADCLRC) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz
(for DAC operation only). The master clock is used to operate the digital filters and the noise shaping
circuits.
In Slave mode the WM8771 has a master clock detection circuit that automatically determines the
relationship between the system clock frequency and the sampling rate (to within +/- 32 system
clocks). If there is a greater than 32 clocks error the interface is disabled and maintains the output
level at the last sample. The master clock must be synchronised with ADCLRC/DACLRC, although
the WM8771 is tolerant of phase variations or jitter on this clock.
SAMPLING
RATE
(DACLRC/
ADCLRC)
128fs
System Clock Frequency (MHz)
192fs
256fs
384fs
512fs
768fs
32kHz
4.096
6.144
8.192
12.288
16.384
24.576
44.1kHz
5.6448
8.467
11.2896 16.9340 22.5792 33.8688
48kHz
6.114
9.216
12.288
18.432
24.576
36.864
96kHz
12.288 18.432
24.576
36.864 Unavailable Unavailable
192kHz
24.576 36.864 Unavailable Unavailable Unavailable Unavailable
Table 6 System Clock Frequencies Versus Sampling Rate
In Master mode BCLK, DACLRC and ADCLRC are generated by the WM8771. The frequencies of
ADCLRC and DACLRC are set by setting the required ratio of MCLK to DACLRC and ADCLRC using
the DACRATE and ADCRATE control bits (Table 7).
ADCRATE[2:0]/ MCLK:ADCLRC/DACLRC
DACRATE[2:0]
RATIO
000
128fs
001
192fs
010
256fs
011
384fs
100
512fs
101
768fs
Table 7 Master Mode MCLK:ADCLRC/DACLRC ratio select
w
PP Rev 2.0 December 2001
14
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