WM8716SEDS 查看數據表（PDF） - Wolfson Microelectronics plc

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WM8716SEDS

High Performance 24-bit, 192kHz Stereo DAC

Wolfson Microelectronics plc 

Production Data

SOFT MUTE

MUT

(REG2, B0)

L

Soft Mute off (normal operation)

H

Soft Mute on (no output)

Table 8 Soft Mute

WM8716

Setting MUT causes the attenuation to ramp from the current value down to 00. The values held in

the attenuation registers are unchanged. When MUT is reset the attenuation will ramp back up to the

previous value. The ramp rate is 128/fs s/0.5dB step.

DIGITAL DE-EMPHASIS

DEM

(REG2, B1)

L

De-emphasis off

H

De-emphasis on

Table 9 Digital De-Emphasis

DAC OPERATION ENABLE

OPE

(REG2,B2)

L

Normal operation

H

DAC output forced to bipolar zero,

irrespective of input data.

Table 10 DAC Operation Enable

AUDIO DATA INPUT FORMAT

I2S

IW1

IW0

(REG3, B0) (REG2, B4) (REG2, B3)

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

Table 11 Audio Data Input Format

AUDIO INTERFACE

16-bit standard right justified

20-bit standard right justified

24-bit standard right justified

24-bit left justified (MSB first)

16-bit I2S

24-bit I2S

20-bit I2S

20-bit left justified (MSB first)

POLARITY OF LR INPUT CLOCK

The left channel data for a particular sample instant is always input first, then the right channel data.

LRP

(REG3, B1)

L

LR High – left channel

LR Low – right channel

H

LR Low – left channel

LR High – right channel

Table 12 Polarity of LR Input Clock

w

PD, Rev 4.2, August 2008

15

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