UPD75218CW-XXX 查看數據表（PDF） - NEC => Renesas Technology

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UPD75218CW-XXX

4-BIT SINGLE-CHIP MICROCOMPUTER

NEC => Renesas Technology 

µPD75218

3.2 NON-PORT PINS

Dual-

Pin

I/O

function pin

Function

Input / output

After reset circuit typeNote

T0 to T9

Output

–––

FIP controller/ Output pins with high withstand voltage Low level

I

T10/S15 to

T13/S12

PH3 to PH0

driver output

pins.

Pull-down

resistor can

be incorpo-

and high current for digit output

(with an on-

chip pull-

Output pins with high withstand voltage down

and high current also used for digit/seg- resistor ) or

ment output

Extra pins can be used as PORTH.

high

impedance

(without a

T14/S11,

T15/S10

–––

rated in bit

units (mask

Output pins with high withstand voltage

and high current also used for digit/

pull-down

resistor)

option).

segment output

Static output also possible.

S9

High withstand-voltage output for segment

output. Static output also possible.

S0 to S8

High withstand-voltage output for segment

output

PPO

Output

–––

Timer/pulse generator pulse output

High

D

impedance

TI0

SCK

SO

Input

P13

Input/output

P01

Input/output

P02

External event pulse input for timer/event counter

Serial clock input/output

Serial data output or serial data input/output

–––

B

Input

F

Input

G

SI

INT4

Input

P03

Serial data input or normal input

Input

B

Input

P00

Edge-detected vectored interrupt input (rising and falling

–––

B

edge detection).

INT0

Input

P10

Edge-detected vectored interrupt input with noise

–––

B

INT1

elimination function (detection edge selection possible).

P11

INT2

Input

P12

Edge-detected testable input (rising edge detection).

–––

B

BUZ

Input/output

P23

Fixed frequency output (for buzzer or system clock

Input

E

trimming).

X1

Input

–––

Crystal/ceramic connection pin for main system clock

–––

–––

oscillation.

X2

–––

External clock input to X1 and its inverted clock input to

X2.

XT1

Input

–––

Crystal connection pin for subsystem clock oscillation.

–––

–––

XT2

–––

External clock input to XT1. Leave XT2 open.

RESET

Input

–––

System reset input (low level active).

–––

B

5

VPRE

–––

–––

FIP controller/driver output buffer power supply.

–––

I

VLOAD

–––

–––

FIP controller/driver pull-down resistor connection pin.

–––

I

VDD

–––

–––

Positive power supply.

VSS

–––

–––

GND potential.

–––

–––

–––

–––

Note The circuit-type codes enclosed in circles indicate that the corresponding circuits have a Schmitt-triggered

input.

8

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