µPD30500, 30500A, 30500B
PIN NAMES
BigEndian:
ColdReset:
ExtRqst:
GND:
GNDP:
Int (0:5):
ModeClock:
Modeln:
NC:
NMI:
RdRdy:
Release:
Reset:
ScCLR:
ScCWE (0:1):
ScDCE (0:1):
ScDOE:
ScLine (0:15):
ScMatch:
ScTCE:
ScTDE:
ScTOE:
ScValid:
ScWord (0:1):
SysAD (0:63):
SysADC (0:7):
SysClock:
SysCmd (0:8):
SysCmdP:
Validln:
ValidOut:
VDD:
VDD:
VDDIO:
VDDOk:
VDDP:
WrRdy:
Endian Mode Select
Cold Reset
External Request
Ground
Quiet GND for PLL
Interrupt Request
Boot Mode Clock
Boot Mode Data In
No Connection
Non-maskable Interrupt Request
Read Ready
Release Interface
Reset
Secondary Cache Block Clear
Secondary Cache Write Enable
Data RAM Chip Enable
Data RAM Output Enable
Secondary Cache Line Index
Secondary Cache Tag Match
Secondary Cache Tag RAM Chip Enable
Secondary Cache Tag RAM Data Enable
Secondary Cache Tag RAM Output Enable
Secondary Cache Valid
Secondary Cache Word Index
System Address/Data Bus
System Address/Data Check Bus
System Clock
System Command/Data Identifier
System Command/Data Identifier Bus Parity
Valid Input
Valid Output
Power Supply (µPD30500)
Power Supply for Processor Core (µPD30500A, 30500B)
Power Supply for Processor I/O (µPD30500A, 30500B only)
VDD is OK
Quiet VDD for PLL
Write Ready
8
Data Sheet U12031EJ4V0DS00