AD871JD 查看數據表（PDF） - Analog Devices

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AD871JD

Complete 12-Bit 5 MSPS Monolithic A/D Converter

Analog Devices 

AD871

VIN

8

DIGITAL

OFFSET

WORD 4

74

8

HC

574

74 4

HC

574

AD568

IBPO

IOUT

RL

ACOM

LCOM

REF COM

1 VINA

AD871

2 VINB

Figure 32. Offset Correction Using the AD568

UNDERSAMPLING USING THE AD871 AND AD9100

The AD871’s on-chip THA optimizes transient response while

maintaining low noise performance. For super-Nyquist (under-

sampling) applications it may be necessary to use an external

THA with fast track-mode slew rate and hold mode settling

time. An excellent choice for this application is the AD9100, an

ultrahigh speed track-and-hold amplifier.

In order to maximize the spurious free dynamic range of the cir-

cuit in Figure 33, it is advantageous to present a small signal to

the input of the AD9100 and then amplify the output to the

AD871’s full-scale input range. This can be accomplished with

a low distortion, wide bandwidth amplifier such as the AD9617.

The circuit uses a gain of 3.5 to optimize S/(N+D).

The peak performance of this circuit is obtained by driving the

AD871 + AD9100 combination with a full-scale input. For

small scale input signals (–20 dB, –40 dB), the AD871 performs

better without the track-and-hold because slew-limiting effects

are no longer dominant. To gain the advantages of the added

track-and-hold, it is important to give the AD871 a full-scale

input.

An alternative to the configuration presented above is to use the

AD9101 track-and-hold amplifier. The AD9101 provides a

built-in post amplifier with a gain of 4, providing excellent ac

characteristics in conjunction with a high level of integration.

As illustrated in Figure 33, it is necessary to skew the AD871

sample clock and the AD9100 sample/hold control. Clock skew

(tS) is defined as the time starting at the AD9100’s transition

into hold mode and ending at the moment the AD871 samples.

The AD871 samples on the rising edge of the sample clock, and

the AD9100 samples on the falling edge of the sample/hold con-

trol. The choice of tS is primarily determined by the settling

time of the AD9100. The droop rate of the AD9100 must also

be taken into consideration. Using these values, the ideal tS is

17 ns. When choosing clock sources, it is extremely important

that the front end track-and-hold sample/hold control is given a

very low jitter clock source. This is not as crucial for the AD871

sample clock, because it is sampling a dc signal.

CLOCK 1

IN

+VS –VS

VIN

RT

Q

RT AD96685

Q

510⍀ 510⍀

–VS

–VS

AD9100

+VS

+5V

3.3␮F

CLOCK 2

IN

10␮F

0.1␮F

0.1␮F

442⍀

127⍀

*

AD9617

*

0.1␮F

AIN AD871

EB

0.1␮F

+VS = 5.0V

–VS = –5.2V

ALL CAPACITORS ARE 0.01␮F

(LOW INDUCTANCE - DECOUPLING)

UNLESS OTHERWISE NOTED.

CLOCK 2

tS = 17ns

CLOCK 1

–VS

T = 200ns

tS

T = 200ns

10␮F

3.3␮F

–5V

*OPTIONAL, SEE

AD9617 DATA SHEET

+5V

0V

+1V

–1V

Figure 33. Undersampling Using the AD871 and AD9100

REV. A

–15–

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