CDP68HC68T1E 查看數據表（PDF） - Intersil

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CDP68HC68T1E

CMOS Serial Real-Time Clock With RAM and Power Sense/Control

Intersil 

Timing Diagrams

MOSI

5

W/R

A6

CDP68HC68T1

A

A0

5

D7O D6O D1N

DON

CE

I

SCK

C

2

4

3

FIGURE 14. WRITE-CYCLE TIMING WAVEFORMS

MOSI

5

W/R

A6

MISO

CE

I

SCK

4

3

A

A0

C

8

D7O

7

D6O DIN

System Diagrams

FIGURE 15. READ-CYCLE TIMING WAVEFORMS

11 12

DON

8

2

AC

LINE

BRIDGE

REGULATOR

VDD POR

INT

LINE

VSYS

CDP68HC68T1

VBATT CPUR

CE

SCK

MOSI

MISO

XTAL IN

VDD

VDD

IRQ

CDP68HC05C8B

RESET

PORT

SCK

MOSI

MISO

NOTE: Example of a system in which power is always on. Clock circuit driven by line input frequency.

FIGURE 16. POWER-ON ALWAYS SYSTEM DIAGRAM

17

FN1547.8

October 29, 2007

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