TC58NS256DC 查看數據表（PDF） - Toshiba

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TC58NS256DC

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

Toshiba 

Sequential Read (1) Timing Diagram

CLE

TC58NS256DC

CE

WE

ALE

RE

I/O1

00H

~I/O8

RY/BY

A0~A7 A9~A16 A17~A24

N N + 1 N + 2 527

012

527

Column Page

address address

tR

tR

N

M

Page M

access

Page M + 1

access

: VIH or VIL

Sequential Read (2) Timing Diagram

CLE

CE

WE

ALE

RE

I/O1

01H

~I/O8

RY/BY

A0~A7 A9~A16 A17~A24

527

012

527

Column Page

address address

tR 256 + 256 + 256 +

tR

N

M

N N+1 N+2

Page M

access

Page M + 1

access

: VIH or VIL

2000-08-27 11/33

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