HIP6012CV 查看數據表（PDF） - Intersil
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HIP6012CV Datasheet PDF : 12 Pages
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HIP6012
OSC
VIN
DRIVER
PWM
COMPARATOR
LO
∆VOSC
-
+
DRIVER
ZFB
VE/A
-
+
ZIN
ERROR REFERENCE
AMP
PHASE
CO
ESR
(PARASITIC)
VOUT
DETAILED COMPENSATION COMPONENTS
C2
C1
R2
ZFB
VOUT
ZIN
C3 R3
R1
COMP
-
FB
+
HIP6012
REF
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
FLC=
------------------1--------------------
2π • LO • CO
FESR=
----------------------1----------------------
2π • (ESR • CO)
The compensation network consists of the error amplifier
(internal to the HIP6012) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180o. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
FZ1 = 2----π-----•----R---1--2-----•----C-----1--
FZ2 = 2----π-----•----(---R-----1----+-1----R-----3----)---•-----C----3--
FP1
=
--------------------------1----------------------------
2π • R2 • C-C----1-1----+•-----CC-----22--
FP2
=
----------------1------------------
2π • R3 • C3
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1ST Zero Below Filter’s Double Pole
(~75% FLC)
3. Place 2ND Zero at Filter’s Double Pole
4. Place 1ST Pole at the ESR Zero
5. Place 2ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak do to the high Q factor of the output filter and is not shown
in Figure 8. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at FP2 with the capabilities of the error
amplifier. The Closed Loop Gain is constructed on the log-log
graph of Figure 8 by adding the Modulator Gain (in dB) to the
Compensation Gain (in dB). This is equivalent to multiplying the
modulator transfer function to the compensation transfer
function and plotting the gain.
100
FZ1 FZ2 FP1 FP2
80
OPEN LOOP
60
ERROR AMP GAIN
40
20LOG
20 (R2/R1)
20LOG
0
(VIN/∆VOSC)
-20
MODULATOR
GAIN
-40
-60
FLC
FESR
10 100 1K 10K 100K
COMPENSATION
GAIN
CLOSED LOOP
GAIN
1M 10M
FREQUENCY (Hz)
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45o.
Include worst case component variations when determining
phase margin.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
7
FN4324.2
December 27, 2004
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