STK14C88-NF35U 查看數據表（PDF） - Simtek Corporation
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STK14C88-NF35U Datasheet PDF : 15 Pages
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nvSRAM OPERATION
STK14C88-NF35U
The STK14C88-NF35U has two separate modes of
operation: SRAM mode and nonvolatile mode. In
SRAM mode, the memory operates as a standard
fast static RAM. In nonvolatile mode, data is trans-
ferred from SRAM to nonvolatile elements (the
STORE operation) or from nonvolatile elements to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
NOISE CONSIDERATIONS
The STK14C88-NF35U is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1μF connected between VCAP
and VSS, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK14C88-NF35U performs a READ cycle
whenever E and G are low and W and HSB are
high. The address specified on pins A0-14 determines
which of the 32,768 data bytes will be accessed.
When the READ is initiated by an address transition,
the outputs will be valid after a delay of tAVQV (READ
cycle #1). If the READ is initiated by E or G, the out-
puts will be valid at tELQV or at tGLQV, whichever is later
(READ cycle #2). The data outputs will repeatedly
respond to address changes within the tAVQV access
time without the need for transitions on any control
input pins, and will remain valid until another address
change or until E or G is brought high, or W or HSB is
brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-7 will be written into the memory if it is valid tDVWH
before the end of a W controlled WRITE or tDVEH
before the end of an E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
POWER-UP RECALL
During power up, or after any low-power condition
(VCAP < VRESET), an internal RECALL request will be
latched. When VCAP once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK14C88-NF35U is in a WRITE state at the
end of power-up RECALL, the SRAM data will be cor-
rupted. To help avoid this situation, a 10K Ohm
resistor should be connected either between W and
system VCC or between E and system VCC.
SOFTWARE NONVOLATILE STORE
The STK14C88-NF35U software STORE cycle is ini-
tiated by executing sequential E controlled READ
cycles from six specific address locations. During
the STORE cycle an erase of the previous nonvola-
tile data is first performed, followed by a program of
the nonvolatile elements. The program operation
copies the SRAM data into nonvolatile memory.
Once a STORE cycle is initiated, further input and
output are disabled until the cycle is completed.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence, or the sequence will be
aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
The software sequence must be clocked with E con-
trolled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
Document Control #ML0066 Rev 2.0
9
Feb, 2008
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