MC14516 查看數據表（PDF） - Motorola => Freescale
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MC14516 Datasheet PDF : 10 Pages
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Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
PE
Cin
Cout
CLOCK
L.S.D.
MC14516B
U/D
R
P0
P1
P2
P3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
PE
Cin
Cout
CLOCK
M.S.D.
MC14516B
U/D
R
P0
P1
P2
P3
fout
BUFFER
P0
P1
P2
P3
P4
P5
P6
P7
CLOCK (fin)
RESET
+VDD
OPEN = COUNT
+VDD
THUMBWHEEL SWITCHES
(OPEN FOR “0”)
+VDD
W RESISTORS = 10 k
fout =
fin
n
NOTE: The programmable frequency divider can be set by applying the desired divide ratio, in binary, to the preset inputs. For example,
the maximum divide ratio of 255 may be obtained by applying a 1111 1111 to the preset inputs P0 to P7. For this divide operation,
both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided.
Figure 4. Programmable Cascaded Frequency Divider
MC14516B
400
MOTOROLA CMOS LOGIC DATA
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