SPT5420 查看數據表（PDF） - Cadeka Microcircuits LLC.
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SPT5420 Datasheet PDF : 8 Pages
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VOLTAGE REFERENCES AND
ANALOG GROUND INPUTS
Three VREFTXX and three VREFBXX inputs set the output
range of the three corresponding groups of DACs
(0 and 1; 2 through 5; 6 and 7). Four RGNDXX inputs set
the output offset voltage of the four corresponding groups
of DACs (0 and 1; 2 and 3; 4 and 5; 6 and 7). The formula
for output swing and offset is presented in the “Analog
Outputs” section below.
ANALOG OUTPUTS VS DIGITAL INPUT
CODE
The output voltage range is equal to twice the difference
between VREFTXX and VREFBXX. The output voltage is
given by:
VOUT
=
2
X
(VREFB
+[VREFT
–
VREFB]
X
) INPUT CODE
8192
–
VRGND
CODE = 0 – 8191
DAC ADDRESSING AND LATCHING
Each DAC has an input latch which receives data from the
data bus, and a DAC latch which receives data from the
input latch. The analog output of each DAC corresponds
to the data in its DAC latch. One of the eight input latches
is addressed by the address lines A(2:0) according to
Table I. While CS and WR are low, the addressed input
latch is transparent and the seven other input latches are
latched. Bringing CS or WR high latches data into the ad-
dressed input latch. While LDAC is low, all eight DAC
latches are transparent. Bringing LDAC high latches data
into the DAC latches. While CS, WR and LDAC are low, both
latches are transparent and input data is transferred
directly to the selected DAC. While CLR is low, all DAC out-
puts are set to their corresponding RGNDXX. Bringing CLR
high returns each DAC’s output to the voltage correspond-
ing to the data in each DAC latch.
Table II summarizes this information, and figures 1a and
1b should be referenced for timing limitations.
POWER SUPPLY SEQUENCING
The sequence in which VDD, VSS and VCC come up is not
critical. The reference inputs, VREFTXX and VREFBXX, must
come on only after VDD and VSS have been established.
However, they may be turned on prior to VCC. The digital
inputs must be driven only after VDD, VSS and VCC have
been established. Reverse the power-on sequence for
power-down.
Table I – DAC Addressing
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Addressed Input
Latch DAC#
0
1
2
3
4
5
6
7
Table II – Control Logic Table
WR CS LDAC CLR Input Latch DAC Latch
0
0
x
1 transparent1
x
1
x
x
1
latched
x
x
1
x
1
latched
x
x
x
0
1
x
transparent
x
x
1
1
x
latched
x
x
x
0 DAC outputs at RGNDXX
Note:
1. Only the input latch addressed by A(2:0) is transparent.
The other input latches are latched.
SPT5420
5
6/26/01
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