SP9504KP 查看數據表（PDF） - Signal Processing Technologies
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SP9504KP Datasheet PDF : 11 Pages
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on-reset. Using this feature, the SP9504 can be
configured such that during power-up, the
second register will be digitally “zeroed”,
producing a zero volt output at each of the four
DAC outputs. This is achieved by powering the
unit up with XFER in a high state. Thus, with no
external circuitry, the SP9504 can be powered
up with the analog outputs at a known, zero volt
output level.
TEMPORARILY FORCING
ALL DAC OUTPUTS TO 0V
Set WR1=1, CS=1, WR2=0, XFER=0. The DAC
registers can be temporarily forced to 1000 0000
0000 by bringing the CLR pin low. This will
force the DAC outputs to 0V, while the CLR pin
remains low. When the CLR pin is brought back
high, the digital code at the DAC registers will
again appear at the DAC's digital inputs, and the
analog outputs will return to theirpreviousvalues.
+3V
Reference GND +5V –5V
VOUT3
VOUT4
VOUT1
1
2
3
4
VOUT4
VSS
VDD
CLR
5 REF IN
6 GND
7 B1/B2
8
9
10
A0
A1
XFER
11 WR2
12 WR1
13 CS
14 VOUT1
VOUT3
DB0
DB1
DB2
DB3
DB4
SP9504
DB5
DB6
DB7
DB8
DB9
DB10
(MSB) DB11
VOUT2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
12–Bit
Data
Bus
VOUT2
(a)
DAC Strobe
Address
Decode &
Control
+3V
Reference GND +5V –5V
VOUT3
VOUT4
VOUT1
1
2
3
4
VOUT4
VSS
VDD
CLR
5 REF IN
6 GND
7 B1/B2
8
9
10
A0
A1
XFER
11 WR2
12 WR1
13 CS
14 VOUT1
VOUT3
DB0
DB1
DB2
DB3
DB4
SP9504
DB5
DB6
DB7
DB8
DB9
DB10
(MSB) DB11
VOUT2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VOUT2
12–Bit
Data
Bus
Address
Decode &
Control
(b)
Figure 3. Latch Control Options — (a) Semi–Transparent Latch Mode; (b) Fully–Transparent Latch Mode
Figure 4. Timing
WR2 H
L
H
CS L
H
WR1 L
140ns, tWR
Loads Input Data to
First Set of Latches
CLR H
L
H
XFER L
H
WR2 L
140ns, t
XFER
Data Transfer from
Input Register to DAC's
SP9504DS/03
SP9504 Quad, 12-Bit, Voltage Output D/A Converter
8
© Copyright 2000 Sipex Corporation
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