SP8853 查看數據表（PDF） - Zarlink Semiconductor Inc

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SP8853

1.3 GHz Professional Synthesiser Data Sheet

Zarlink Semiconductor Inc 

SP8853

Data Sheet

RF INPUT 10

RF INPUT 11

16/17 OR 8/9

CONTROL

A COUNT

1LOGIC

M COUNT

fPD

1LOGIC

PHASE

DETECTOR

F1/F2 13

DATA 14

15

CLOCK

ENABLE 16

POWER 6

DOWN

DATA

INPUT

LOGIC

2-BIT

SR

4 BIT

N0 N3

N0 N12

13 BIT

15 BIT

2 BIT

DUAL

F1/F2

DATA

BUFFER

1 BIT

N4 N18

N19 N20

N21

22 BIT SHIFT REGISTER

N13

1 BIT

N14 N15

2 BIT

SINGLE

REFERENCE

BUFFER

CHARGE

PUMP 1

3 PD1

CHARGE

PUMP 2

24 RPD

28 Cd

25 PD2

27 LOCK

DETECT

R

COUNT

REFERENCE

DIVIDER

20 21

CRYSTAL

LOGIC

fREF

5 FREF*

OUTPUT

INTERFACE

4 FPD*

*FREF and FPD outputs are reversed by the phase detector

sense bit in the F1/F2 programming word. The pin allocations

shown are correct when the sense bit is low (see Table 2 and Fig. 7).

Fig. 2 SP8853 block diagram

PD1

3

CHARGE

PUMP 1

CHARGE PUMP 1 DISABLE

(SEE TABLE 4)

VCC

Output current at pin 27 is proportional to

voltage difference between pins 25 and 28,

45k

IMAX = 625µA

−

31

CHARGE

+

PUMP 2

10k

31

TRANSCONDUCTANCE

fPD

PHASE

AMPLIFIER

31 BUFFER

fREF

DETECTOR

45k

−

+

−

+

DUAL VOLTAGE

COMPARATOR

27

LOCK DETECT

24

25

RPD PD2

28

Cd

Fig. 3 Detailed block diagram of lock detect circuit

2

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