CXD1812 查看數據表（PDF） - Sony Semiconductor
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CXD1812 Datasheet PDF : 56 Pages
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CXD1812Q/R
2-9. DECCTL1 (decoder control 1) register (address 08HEX)
bit 7:
ENSBQRD (enable subcode-Q read)
CRC of subcode-Q is checked by taking in the subcode from DSP. Sub CPU can read subcode-Q
data from the SUBQ register.
bit 6:
RESERVED
bit 5 to 3: DECCMD2 to 0 (decoder commands 2 to 0)
DECCMD2
"L"
"L"
"L"
"L"
"H"
"H"
DECCMD1
"L"
"L"
"H"
"H"
"L"
"H"
DECCMD0
"L"
"H"
"L"
"H"
"H"
"H"
Decoder command
Decoder disable
Monitor only
Write only
Real-time correction
Raw subcode buffer
CD-DA
bit 2 to 0: RESERVED
2-10. XFRMOD (transfer mode) register (address 09HEX)
bit 7:
ENHINTCT (enable auto HINT upon start of packet command transfer)
High: When packet command transfer starts, there is an interrupt request to the host.
Low: When the transfer above starts, there is no interrupt request to the host.
bit 6:
ENHINTDT (enable auto HINT upon start of data transfer)
High: When data transfer with the host starts, there is an interrupt request to the host.
Low: When the transfer above starts, there is no interrupt request to the host.
bit 5:
ENMDMA (enable multiword DMA)
This bit is valid for DMA transfer.
High: DMA transfer is executed in the multiword mode.
Low: DMA transfer is executed in the single-word mode.
bit 4:
ENDMABIT (enable ATAPI feature register DMA bit)
bit 3:
PIOSEL (PIO transfer mode select)
Transfer mode is determined as shown below from the combination of these bits and the DMA bit
(bit 0) of ATAPI feature register.
PIOSEL
"H"
"L"
"L"
"L"
ENDMABIT
"X"
"H"
"H"
"L"
DMA
"X"
"H"
"L"
"X"
Transfer Mode
PIO
DMA
PIO
DMA
bit 2:
AUTOWAIT (enable auto wait state)
This bit is valid for PIO transfer.
High: In the cases below, the REDY pin is set low and a wait is automatically applied to the host.
Transfer to host: When the host asserts the XHRD signal while the data FIFO is empty.
Transfer from host: When the host asserts the XHWR signal while the data FIFO is full.
Low: The wait state above does not occur.
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