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SI4702-C19 查看數據表(PDF) - Silicon Laboratories

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SI4702-C19 Datasheet PDF : 46 Pages
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Si4702/03-C19
Register 07h. Test 1
Bit D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name XOSCEN AHIZEN
Reserved
Type R/W
R/W
R/W
Reset value = 0x0100
Bit
Name
Function
15
XOSCEN Crystal Oscillator Enable.
0 = Disable (default).
1 = Enable.
The internal crystal oscillator requires an external 32.768 kHz crystal as shown in
2. "Typical Application Schematic" on page 14. The oscillator must be enabled before
powerup (ENABLE = 1) as shown in Figure 9, “Initialization Sequence,” on page 21. It
should only be disabled after powerdown (ENABLE = 0). Bits 13:0 of register 07h
must be preserved as 0x0100 while in powerdown and as 0x3C04 while in powerup.
Refer to Si4702/03 Internal Crystal Oscillator Errata.
14
AHIZEN
Audio High-Z Enable.
0 = Disable (default).
1 = Enable.
Setting AHIZEN maintains a dc bias of 0.5 x VIO on the LOUT and ROUT pins to pre-
vent the ESD diodes from clamping to the VIO or GND rail in response to the output
swing of another device. Register 07h containing the AHIZEN bit must not be written
during the powerup sequence and high-Z only takes effect when in powerdown and
VIO is supplied. Bits 13:0 of register 07h must be preserved as 0x0100 while in pow-
erdown and as 0x3C04 while in powerup.
13:0
Reserved Reserved.
If written, these bits should be read first and then written with their pre-existing val-
ues. Do not write during powerup.
30
Rev. 1.1

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