CS8405A-IS 查看數據表（PDF） - Cirrus Logic
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CS8405A-IS Datasheet PDF : 37 Pages
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11.PIN DESCRIPTION - HARDWARE MODE
COPY / C
1
VL2+
2
EMPH
3
SFMT0
4
SFMT1
5
VD+
6
DGND4
7
DGND3
8
RST
9
APMS
10
TCBLD
11
ILRCK
12
ISCLK
13
SDIN
14
CS8405A
28
ORIG
27
VL4+
26
TXP
25
TXN
24
H/S
23
VL+
22
DGND
21
OMCK
20
VL3+
19
AUDIO
18
U
17
V
16
CEN
15
TCBL
VD+
VL+
VL2+
VL3+
VL4+
DGND
DGND3
DGND4
RST
H/S
TXN
TXP
6 Digital Power (Input) - Digital core power supply. Typically +5.0 V.
23 Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V. All VL+ pins must be
2 at the same voltage.
20
27
22 Digital Ground (Input) - Ground for the digital section.
8
7
9 Reset (Input) - When RST is low, the CS8405A enters a low power mode and all internal states are
reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks
are stable in frequency and phase. This is particularly true in hardware mode with multiple CS8405A
devices, where synchronization between devices is important.
24 Hardware/Software Control Mode Select (Input) -Determines the method of controlling the opera-
tion of the CS8405A, and the method of accessing CS and U data. In software mode, device control
and CS and U data access is primarily through the control port, using a microcontroller. Hardware
mode provides an alternate mode of operation, and access to CS and U data is provided by dedi-
cated pins. This pin should be permanently tied to VL+ or DGND.
25 Differential Line Drivers (Output) - These pins transmit biphase encoded data. The drivers are
26 pulled low while the CS8405A is in the reset state.
DS469F2
29
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